The present invention relates to a semiconductor design technique, and more particularly, to a power-up signal generating circuit and an integrated circuit using the same for generating a power-up signal.
In general, an integrated circuit performs a specific operation according to a various operation mode, and maintains a voltage level of an internal voltage outputted from an internal power circuit as a ground voltage level to minimize a current consumption in a deep power down (DPD) mode. The integrated circuit has a circuit for generating a power-up signal as a start control signal which is used for initializing an internal circuit when a power voltage provided from an external is increased to a predetermined level and stabilized.
In a normal operation mode, the power-up signal is activated, resets a latch of an internal circuit, activates an internal power circuit, and controls an internal voltage to be supplied with a predetermined voltage level. Moreover, in the DPD mode, the power-up signal is inactivated, disables the internal power circuit, and controls the internal voltage to be maintained as a ground voltage level.
FIG. 1 is a block diagram illustrating a conventional power-up signal generating circuit.
As shown, a conventional power-up signal generating circuit includes a detecting unit 110 and a signal generating unit 120. The detecting unit 110 outputs a bias signal BIAS having a voltage level corresponding to an external power voltage VDD in response to a DPD signal. The signal generating unit 120 generates a power-up signal PWRUP_PRE having a logic level corresponding to the external power voltage VDD in response to the DPD signal and the bias signal BIAS.
A detailed configuration and operation of the conventional power-up signal generating circuit will be described below.
The detecting unit 110 generates a bias signal BIAS having a voltage level corresponding to the external power voltage VDD based on a normal operation mode and a DPD mode in response to a DPD signal. That is, when the DPD signal is a logic low, the detecting unit 110 generates the bias signal BIAS under the normal operation mode, and when the DPD signal is a logic high, the detecting unit 110 generates the bias signal under the DPD mode.
The detecting unit 110 includes a first PMOS transistor MP1, a plurality of first voltage drop elements R1, R2 and R3, a plurality of second voltage drop elements R4, R5 and R6, a first NMOS transistor MN1 and a capacitor CAP1. The first PMOS transistor MP1 is coupled between the external power voltage VDD and a first node N1, and controlled by the DPD signal. The plurality of first voltage drop elements R1, R2 and R3 are coupled between the first node N1 and an output terminal NO of the bias signal BIAS. The plurality of second voltage drop elements R4, R5 and R6 are coupled between the output terminal NO of the bias signal BIAS and a ground voltage VSS terminal. The first NMOS transistor NM1 is connected between a ground voltage VSS terminal and the output terminal NO of the bias signal BIAS, and controlled by the DPD signal. The capacitor CAP1 is coupled between the ground voltage VSS terminal and the output terminal NO of the bias signal.
The signal generating unit 120 generates a power-up signal PWRUP_PRE having a logic level corresponding to the external power voltage VDD in response to the DPD signal and the bias signal BIAS.
The signal generating unit 120 includes a plurality of PMOS transistors MP2, MP3 and MP4, a plurality of NMOS transistors MN2 and MN3, a NOR logic circuit NOR1, a first inverter INV1 and a second inverter INV2. The plurality of PMOS transistors MP2, MP3 and MP4 are connected between the external power voltage VDD and a second node N2. Gates of the plurality of PMOS transistors MP2, MP3 and MP4 are coupled to the ground voltage VSS terminal. A plurality of NMOS transistors MN2 and MN3 are coupled between the second node N2 and the ground voltage VSS terminal in series, and are controlled by the bias signal BIAS. The NAND logic circuit NOR1 receives output signals of the second node N2 and the DPD signal. The first inverter INV1 inverts an output signal of the NOR logic circuit NOR1. The second inverter INV2 inverts an output signal of the first inverter INV1.
When the DPD signal is a logic low level, the power-up signal generating circuit operates under a normal operation mode. Because the first PMOS transistor MP1 controlled by the DPD signal is turned on, a voltage level of the output terminal NO depends on a resistance value ratio of first voltage drop elements R1, R2 and R3 and second voltage drop elements R4, R5 and R6. Accordingly, when a power is supplied from an external and a voltage level of an external power voltage VDD is increased from the ground voltage level to the external power voltage VDD, the voltage level of the output terminal NO depends on a resistance value ratio of voltage drop elements. That is, a bias signal BIAS output from the output terminal NO is output by dividing the voltage of a supply power through the voltage drop elements.
Moreover, during a start time of a power supply, a voltage level of the second node N2 of the signal generating unit 120 maintains the voltage level supplied from the external power voltage VDD because the PMOS transistors MP2, MP3 and MP4 of the signal generating unit 120 are turned on. If the voltage level of the bias signal BIAS is increased higher than a predetermined level, the NMOS transistors MN2 and MN3 of the signal generating unit 120 are turned on, and the voltage level of the second node N2 is decreased to the ground voltage level VSS.
The first NOR logic circuit NOR1 outputs an output signal having a logic level in response to the voltage level of the output signal of the second node N2 because the DPD signal is a logic low level. Finally, a power-up signal PWRUP_PRE is output through the first inverter INV1 and the second inverter INV2. In short, if the voltage level of the external power voltage VDD is increased higher than a predetermined level, the power-up signal PWRUP_PRE is activated and output as a logic high level.
And then, the signal level of the DPD signal is changed from a logic low level to a logic high level, and the power-up signal generating circuit operates under DPD mode. Since the first PMOS transistor MP1 controlled by the DPD signal is turned off and the first NMOS transistor MN1 is turned on, the voltage level of the output terminal NO is decreased to the ground voltage VSS. That is, the bias signal BIAS is decreased to the voltage level of the ground voltage VSS. Accordingly, the NMOS transistors MN2 and MN3 of the signal generating unit 120 are turned off and the voltage level of the second node N2 is increased to a level of the external power voltage VDD.
Because the DPD signal is a logic high level, the first NOR logic circuit NOR1 outputs a logic low level irrespective of the voltage level of the output signal from the second node N2. Finally, the power-up signal PWRUP_PRE is output through the first inverter INV1 and the second inverter INV2. That is, the power-up signal PWRUP_PRE is inactivated and output as the logic low level.
On the contrary, when the DPD mode is changed to a normal operation mode, because the DPD signal is transitioned from a logic high level to a logic low level, the first PMOS transistor MP1 is turned on and the voltage level of the output terminal NO is increased. That is, the voltage level of the bias signal BIAS is increased higher than a predetermined level, the NMOS transistors MN2 and MN3 of the signal generating unit 120 are turned on, and the second node N2 is decreased to the ground voltage level VSS.
Because it takes time to sufficiently charge a capacitor which is coupled to the output terminal NO, the turn-on time of the NMOS transistors MN2 and MN3 is delayed for a predetermined time. Accordingly, the power-up signal PWRUP_PRE is not activated directly and is delayed for a predetermined time.